1. Field of the Invention
The present invention relates to a technology for supporting the design of a large-scale integrated circuit (LSI).
2. Description of the Related Art
Timing design is a process for estimating a circuit delay of an LSI, executing optimization, and verifying that the delay is within a range required for the normal operation of the LSI. Timing design is indispensable for guaranteeing that a fabricated LSI operates normally, and is very important because the timing design includes a large amount of work and accounts for a large percentage of the process steps for designing the LSI. To reduce the time required for designing an LSI, first, facilitating reduction of the number of process steps for the timing design is necessary.
In LSI design in recent years, for the reasons of reduction of power consumption, reuse of modules, etc., restrictions on complicated timing design are often required. For example, reduction of power consumption is generally facilitated by using a low clock frequency for the parts that do not need to operate fast by dividing the original frequency, and by stopping the supply of unnecessary clock by inserting a clock gate. Because one LSI is used for a plurality of devices, a plurality of operation modes each of which having a timing condition different from that of others may be prepared. Therefore, the restriction on the timing design of an LSI often becomes complicated.
For an LSI to operate at a target frequency, two types of timing restrictions, a set-up restriction and a hold restriction need to be complied with. In general, the timing at which a signal transmitted from a flip flop (FF) on the transmitting side arrives at an FF on the receiving side must be after the present clock and before the next clock. The hold restriction and the set-up restriction respectively mean to guarantee that the arrival of a signal occurs after the present clock and that the arrival of a signal occurs before the next clock, and respectively determine the minimum value and the maximum value of propagating time of the signal.
In a conventional common design flow, after the timing restriction between FFs has been derived and a timing optimizing-arrangement has executed assuming that all FFs receive a clock at the same time, a clock tree is constructed such that skews (the difference in clock arrival time between FFs) are respectively minimized.
FIG. 7 is a diagram showing an example of a clock tree. The thick lines indicate clock paths, the thin lines indicate data paths, and “CS” indicates a clock source. When a clock tree 700 is constructed, the skew in a group G constituted of an FF1, an FF3, . . . located at ends of the clock tree that constitutes a clock generating circuit needs to be zero.
A data path DP is a bus that outputs data from the FF1 to an FF2 (for example, a dividing circuit or a clock gate) that is not located at an end of the clock tree. In this case, the skew is adjusted after arrangement and wiring. As a conventional technique that adjusts a skew after arrangement and wiring, Japanese Patent Application Laid-Open No. 2004-185466 can be listed.
When arrangement and wiring are executed and the clock tree 700 is simply constructed after completing logic synthesis, a timing error can be discovered early by performing static timing analysis (STA). Thereby, the clock tree is re-generated by imposing the timing restriction on the FFs and the error can be corrected.
However, in the clock tree 700 shown in FIG. 7, though the FF1 and the FF3 are in the same group, the FF3 starts operating after the FF2 has started operating into which data has been inputted from the FF1 through the data path DP and, therefore, a skew is generated between the FF1 and the FF3. Therefore, due to the presence of the data path DP, a problem has been arisen that compliance with the timing restriction may be difficult.
As described above, when the timing restriction still remains being not complied with after arrangement and wiring, correction must be executed according to an engineering change order (ECO). However, in the correction after arrangement and wiring, a problem has been arisen that the labor of the designers is increased and the time required for designing becomes longer because of the returned design.
As described above, when the clock tree 700 is simply constructed after completing logic synthesis, an STA analysis is performed to detect timing errors. However, in general, an STA analysis covers all the paths. When the timing of some of the FFs has been respectively changed, the STA analysis needs to be performed on all the paths one by one because other paths may also be influenced. Therefore, because an STA analysis is necessary for each correction of the clock timing when the clock tree is constructed after completing logic synthesis, a problem has arisen that the time required for designing becomes longer.